Memory Mapped I/O

Memory Mapped I/O

๐Ÿ“ฆ ์ „์ฒด ๋ฉ”๋ชจ๋ฆฌ ๋งต ๊ตฌ์กฐ (0x0000_0000 ~ 0xFFFF_FFFF)

STM32๋Š” ์ฃผ์†Œ ๊ณต๊ฐ„์„ 512MB ๋‹จ์œ„๋กœ 8๊ฐœ์˜ ๋ธ”๋ก์œผ๋กœ ๋‚˜๋ˆ•๋‹ˆ๋‹ค:

์ฃผ์†Œ ๋ฒ”์œ„ ๋ธ”๋ก ์„ค๋ช…
0x0000_0000 ~ 0x1FFF_FFFF Block 0 Code ์˜์—ญ (Flash, Boot Memory)
0x2000_0000 ~ 0x3FFF_FFFF Block 1 SRAM ์˜์—ญ
0x4000_0000 ~ 0x5FFF_FFFF Block 2 Peripherals (๋ ˆ์ง€์Šคํ„ฐ)
0x6000_0000 ~ 0x7FFF_FFFF Block 3 FSMC bank1 & bank2 (์™ธ๋ถ€ ๋ฉ”๋ชจ๋ฆฌ ์ธํ„ฐํŽ˜์ด์Šค)
0x8000_0000 ~ 0x9FFF_FFFF Block 4 FSMC bank3 & bank4
0xA000_0000 ~ 0xBFFF_FFFF Block 5 FSMC ๋ ˆ์ง€์Šคํ„ฐ
0xC000_0000 ~ 0xDFFF_FFFF Block 6 ์‚ฌ์šฉ๋˜์ง€ ์•Š์Œ
0xE000_0000 ~ 0xFFFF_FFFF Block 7 Cortex-M3 ๋‚ด๋ถ€ ์‹œ์Šคํ…œ ๋ฐ ๋””๋ฒ„๊ทธ์šฉ ๋ ˆ์ง€์Šคํ„ฐ

๐Ÿ”ธ Block 0 (Code ์˜์—ญ) ์ƒ์„ธ

์ฃผ์†Œ ์„ค๋ช…
0x0000_0000 Flash, System Memory, or SRAM์œผ๋กœ alias ๋จ (BOOT ํ•€์— ๋”ฐ๋ผ ๋‹ฌ๋ผ์ง)
0x0800_0000 ~ 0x080F_FFFF Flash ๋ฉ”๋ชจ๋ฆฌ
0x1FFF_0000 ~ 0x1FFF_7A0F System Memory, OTP, Option Bytes ๋“ฑ
0x1FFF_C000 ~ 0x1FFF_FFFF Option Bytes, Reserved ๋“ฑ

๐Ÿ”ธ Block 1 (SRAM ์˜์—ญ) ์ƒ์„ธ

์ฃผ์†Œ ์„ค๋ช…
0x2000_0000 ~ 0x2001_BFFF SRAM (112KB)
0x2001_C000 ~ 0x2001_FFFF SRAM (16KB)
0x2002_0000 ~ 0x3FFF_FFFF Reserved (bit-band alias ์˜์—ญ ํฌํ•จ)

๐Ÿ’ก Bit-Banding: ๋น„ํŠธ๋ฅผ ๊ฐœ๋ณ„์ ์œผ๋กœ ๋‹ค๋ฃจ๊ธฐ ์œ„ํ•ด ํŠน๋ณ„ํžˆ ๋งคํ•‘๋œ ์ฃผ์†Œ ์˜์—ญ์ž…๋‹ˆ๋‹ค.


๐Ÿ”ธ Block 2 (Peripherals ์˜์—ญ) ์ƒ์„ธ

์ฃผ์†Œ ์ฃผ๋ณ€์žฅ์น˜
0x4000_0000 ~ 0x4000_03FF TIM2, TIM3, TIM4 ๋“ฑ
0x4001_0000 ~ 0x4001_FFFF USART1, SPI1, ADC1~3 ๋“ฑ
์ด 0x4000_0000 ~ 0x5006_03FF ๋ชจ๋“  AHB/APB ์žฅ์น˜๋“ค์ด ์—ฌ๊ธฐ์— ์œ„์น˜

๐Ÿ”ธ Block 3 & 4 (FSMC External Memory ์˜์—ญ)

์ด ์˜์—ญ์€ **์™ธ๋ถ€ ๋ฉ”๋ชจ๋ฆฌ (PSRAM, NOR, NAND ๋“ฑ)**๋ฅผ ์—ฐ๊ฒฐํ•˜๋Š” FSMC ์ปจํŠธ๋กค๋Ÿฌ์˜ bank๋ณ„ ์ฃผ์†Œ์ž…๋‹ˆ๋‹ค:

์ฃผ์†Œ ๋ฒ”์œ„ ์—ฐ๊ฒฐ ์žฅ์น˜
0x6000_0000 ~ 0x63FF_FFFF FSMC bank1 NOR/PSRAM 1
0x6400_0000 ~ 0x67FF_FFFF FSMC bank1 NOR/PSRAM 2
0x6800_0000 ~ 0x6BFF_FFFF FSMC bank1 NOR/PSRAM 3
0x6C00_0000 ~ 0x6FFF_FFFF FSMC bank1 NOR/PSRAM 4
0x7000_0000 ~ 0x7FFF_FFFF FSMC bank2 NAND
0x8000_0000 ~ 0x8FFF_FFFF FSMC bank3 NAND

๐Ÿ”ธ Block 7 (Cortex-M3 ๋‚ด๋ถ€ ์˜์—ญ)

์ฃผ์†Œ ๋ฒ”์œ„ ์„ค๋ช…
0xE000_0000 ~ 0xE00F_FFFF NVIC, SCB, SysTick ๋“ฑ
0xE004_2000 ๋“ฑ ๋””๋ฒ„๊น…, ITM, DWT ๋“ฑ ๋””๋ฒ„๊ทธ ๋ชจ๋“ˆ

์ด ๋ฉ”๋ชจ๋ฆฌ ๋งต์€ ๋ ˆ์ง€์Šคํ„ฐ ์ ‘๊ทผ, DMA ์„ค์ •, Flash ์ ‘๊ทผ, SRAM ์ œ์–ด, ๋ถ€ํŠธ ๋™์ž‘ ๋“ฑ STM32๋ฅผ ์ •ํ™•ํžˆ ๋‹ค๋ฃจ๊ธฐ ์œ„ํ•œ ํ•ต์‹ฌ ์ •๋ณด์ž…๋‹ˆ๋‹ค.


ํ•„์š”ํ•˜๋ฉด ๊ฐ ๋ธ”๋ก๋ณ„๋กœ ์ถ”๊ฐ€ ์„ค๋ช…์ด๋‚˜ ์˜ˆ์ œ ์ฝ”๋“œ๋„ ์ œ๊ณต ๊ฐ€๋Šฅํ•ฉ๋‹ˆ๋‹ค.

ํŠน์ • ์˜์—ญ์—์„œ ์ž์„ธํžˆ ์•Œ๊ณ  ์‹ถ์€ ๋ถ€๋ถ„์ด ์žˆ๋‚˜์š”?

๋‚˜์˜ ๋ง:

memory mapped i/o ์ž–์•„

ChatGPT์˜ ๋ง:

๋งž์Šต๋‹ˆ๋‹ค, ์ด STM32 ๋ฉ”๋ชจ๋ฆฌ ๊ตฌ์กฐ๋Š” Memory-Mapped I/O (MMIO) ๊ตฌ์กฐ๋ฅผ ๋”ฐ๋ฆ…๋‹ˆ๋‹ค. ์•„๋ž˜์—์„œ ๊ฐœ๋…๋ถ€ํ„ฐ STM32์—์„œ์˜ ์ ์šฉ๊นŒ์ง€ ํ•ต์‹ฌ์„ ์ •๋ฆฌํ•ด ๋“œ๋ฆฌ๊ฒ ์Šต๋‹ˆ๋‹ค:


โœ… Memory-Mapped I/O๋ž€?

Memory-Mapped I/O๋Š” ์ฃผ๋ณ€ ์žฅ์น˜ (GPIO, USART, TIM ๋“ฑ)์˜ ๋ ˆ์ง€์Šคํ„ฐ๋ฅผ ๋ฉ”๋ชจ๋ฆฌ ์ฃผ์†Œ ๊ณต๊ฐ„์— ์ง์ ‘ ๋งคํ•‘ํ•ด์„œ ์ผ๋ฐ˜ ๋ฉ”๋ชจ๋ฆฌ์ฒ˜๋Ÿผ ์ ‘๊ทผํ•˜๋Š” ๋ฐฉ์‹์ž…๋‹ˆ๋‹ค.

์ฆ‰,

c
๋ณต์‚ฌํŽธ์ง‘
#define GPIOA_MODER  (*(volatile uint32_t*)0x40020000)
GPIOA_MODER = 0x00000001;

์ฒ˜๋Ÿผ ๋ฉ”๋ชจ๋ฆฌ์— ๊ฐ’์„ ์“ฐ๋Š” ๊ฒƒ์ฒ˜๋Ÿผ ๋ ˆ์ง€์Šคํ„ฐ๋ฅผ ์ œ์–ดํ•˜๋Š” ๋ฐฉ์‹์ž…๋‹ˆ๋‹ค.


โœ… STM32์—์„œ์˜ MMIO ์˜ˆ์‹œ

STM32์—์„œ๋Š” Block 2 (0x4000_0000 ~ 0x5FFF_FFFF)๊ฐ€ ๋ฐ”๋กœ ์ด MMIO๋ฅผ ์œ„ํ•œ ์ฃผ๋ณ€์žฅ์น˜ ๋ ˆ์ง€์Šคํ„ฐ ์˜์—ญ์ž…๋‹ˆ๋‹ค.

์žฅ์น˜ ์‹œ์ž‘ ์ฃผ์†Œ ์˜ˆ์‹œ ์„ค๋ช…
GPIOA 0x4002_0000 ํฌํŠธ A ์ œ์–ด
USART2 0x4000_4400 ์‹œ๋ฆฌ์–ผ ํ†ต์‹  ์ œ์–ด
TIM2 0x4000_0000 ํƒ€์ด๋จธ ์ œ์–ด
RCC 0x4002_3800 ํด๋Ÿญ ์„ค์ •

โœ… ์™œ MMIO๋ฅผ ์‚ฌ์šฉํ• ๊นŒ?

๋ฐฉ์‹ ํŠน์ง•
MMIO CPU๊ฐ€ ๋ฉ”๋ชจ๋ฆฌ์ฒ˜๋Ÿผ ์žฅ์น˜ ๋ ˆ์ง€์Šคํ„ฐ์— ์ ‘๊ทผํ•จ. Load/Store ๋ช…๋ น ์‚ฌ์šฉ.
Port-Mapped I/Oย (x86์—์„œ ์‚ฌ์šฉ) ํŠน๋ณ„ํ•œ I/O ๋ช…๋ น ์‚ฌ์šฉ (in,ย out)

STM32๋Š” MMIO ๋ฐฉ์‹๋งŒ ์ง€์›ํ•ฉ๋‹ˆ๋‹ค. ์žฅ์ ์€:

  • CPU ์ž…์žฅ์—์„œ I/O๋„ ๋ฉ”๋ชจ๋ฆฌ์ฒ˜๋Ÿผ ์ฝ๊ณ  ์”€
  • ์ฃผ์†Œ ๊ณต๊ฐ„ ํ†ตํ•ฉ ๊ด€๋ฆฌ
  • ๊ณ ์† ์ฒ˜๋ฆฌ (๋ฒ„์Šค์— ์ง์ ‘ ์—ฐ๊ฒฐ๋จ)

โœ… STM32 MMIO ์ž‘๋™ ๋ฐฉ์‹ ๊ทธ๋ฆผ

STM32 ๋‚ด๋ถ€ ๊ตฌ์กฐ๋Š” ๋‹ค์Œ๊ณผ ๊ฐ™์€ ํ๋ฆ„์ž…๋‹ˆ๋‹ค:

๋ณต์‚ฌํŽธ์ง‘
[ CPU ]
   โ†“
[ BUS (AHB/APB) ]
   โ†“
[ ์ฃผ์†Œ ๋””์ฝ”๋” ] โ†’ 0x4002_0000 = GPIOA
   โ†“
[ ์žฅ์น˜ ๋ ˆ์ง€์Šคํ„ฐ ]


โœ… ์˜ˆ์ œ: GPIOA ํ•€ ์ถœ๋ ฅ ์ œ์–ด (MMIO ์ง์ ‘ ์ ‘๊ทผ)

c
๋ณต์‚ฌํŽธ์ง‘
#define RCC_AHB1ENR   (*(volatile uint32_t*)0x40023830)
#define GPIOA_MODER   (*(volatile uint32_t*)0x40020000)
#define GPIOA_ODR     (*(volatile uint32_t*)0x40020014)

void gpio_init(void) {
    RCC_AHB1ENR |= (1 << 0);        // GPIOA ํด๋Ÿญ ํ™œ์„ฑํ™”
    GPIOA_MODER |= (1 << 10);       // PA5๋ฅผ ์ถœ๋ ฅ ๋ชจ๋“œ๋กœ
}

void gpio_write_high(void) {
    GPIOA_ODR |= (1 << 5);          // PA5 ์ถœ๋ ฅ High
}


โœ… ์š”์•ฝ

ํ•ญ๋ชฉ ์„ค๋ช…
MMIO๋ž€? ์ฃผ๋ณ€์žฅ์น˜ ๋ ˆ์ง€์Šคํ„ฐ๋ฅผ ๋ฉ”๋ชจ๋ฆฌ ์ฃผ์†Œ์ฒ˜๋Ÿผ ์ง์ ‘ ์ ‘๊ทผ
STM32 ์ ์šฉ ์ฃผ์†Œ 0x4000_0000 ~ 0x5FFF_FFFF (Block 2)
์ ‘๊ทผ ๋ฐฉ๋ฒ• C ํฌ์ธํ„ฐ๋ฅผ ์ด์šฉํ•ด ์ง์ ‘ ๋ ˆ์ง€์Šคํ„ฐ ์ฃผ์†Œ์— ์ ‘๊ทผ
์žฅ์  ๋น ๋ฅด๊ณ  ์ผ๊ด€๋œ ์ ‘๊ทผ ๋ฐฉ์‹, ๊ฐ„๊ฒฐํ•œ ํ•˜๋“œ์›จ์–ด ์ œ์–ด

ํ•„์š”ํ•˜๋ฉด ์ฃผ๋ณ€์žฅ์น˜๋ณ„ MMIO ์ฃผ์†Œ ์ •๋ฆฌํ‘œ๋‚˜, ์ง์ ‘ ์ ‘๊ทผ ๋Œ€์‹  CMSIS๋ฅผ ์‚ฌ์šฉํ•˜๋Š” ๊ตฌ์กฐ๋„ ์ •๋ฆฌํ•ด ๋“œ๋ฆด ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค. ํŠน์ • ์žฅ์น˜๋ฅผ ์˜ˆ๋กœ ๋“ค์–ด๋ณผ๊นŒ์š”?

๋‚˜์˜ ๋ง:

block2 ๋งŒ memory mapped i/o์•ผ?

ChatGPT์˜ ๋ง:

์•„์ฃผ ์ข‹์€ ์งˆ๋ฌธ์ž…๋‹ˆ๋‹ค. ๊ฒฐ๋ก ๋ถ€ํ„ฐ ๋งํ•˜๋ฉด:

๐ŸŸจ Block 2(0x4000_0000 ~ 0x5FFF_FFFF) ์˜์—ญ์ด ๋Œ€ํ‘œ์ ์ธ Memory-Mapped I/O ์˜์—ญ์ด์ง€๋งŒ,

**๐ŸŸฅ Block 7(0xE000_0000 ~ 0xFFFF_FFFF)**๋„ Memory-Mapped I/O ๋ฐฉ์‹์œผ๋กœ ๋™์ž‘ํ•ฉ๋‹ˆ๋‹ค.


โœ… Memory-Mapped I/O๊ฐ€ ์ ์šฉ๋œ ์˜์—ญ

๋ธ”๋ก ์ฃผ์†Œ ๋ฒ”์œ„ ์„ค๋ช… MMIO ์—ฌ๋ถ€
Block 2 0x4000_0000 ~ 0x5FFF_FFFF APB/AHB ๋ฒ„์Šค๋ฅผ ํ†ตํ•œย ์™ธ๋ถ€ ์ฃผ๋ณ€์žฅ์น˜ย (GPIO, USART ๋“ฑ) โœ… O
Block 7 0xE000_0000 ~ 0xE00F_FFFF System Control Block (SCB),ย NVIC,ย SysTick,ย Debug ๋“ฑ โœ… O
๊ธฐํƒ€ ์ผ๋ถ€ Flash ์ปจํŠธ๋กค๋Ÿฌ, Option Bytes Flash interface (write/erase ์ œ์–ด์šฉ ๋ ˆ์ง€์Šคํ„ฐ) โœ… O (๊ฐ„์ ‘์ ์œผ๋กœ)

โŒ MMIO๊ฐ€ ์•„๋‹Œ ์˜์—ญ ์˜ˆ์‹œ

๋ธ”๋ก ์ฃผ์†Œ ๋ฒ”์œ„ ์„ค๋ช… MMIO ์—ฌ๋ถ€
Block 0 0x0000_0000 ~ 0x1FFF_FFFF Flash, Boot ROM, alias ์˜์—ญ โŒ (์ผ๋ฐ˜ ๋ฉ”๋ชจ๋ฆฌ)
Block 1 0x2000_0000 ~ 0x3FFF_FFFF SRAM โŒ (์ผ๋ฐ˜ ๋ฉ”๋ชจ๋ฆฌ)
Block 3~5 FSMC ์˜์—ญ (0x6000_0000 ์ด์ƒ) ์™ธ๋ถ€ ๋ฉ”๋ชจ๋ฆฌ ์ธํ„ฐํŽ˜์ด์Šค (SRAM, NAND ๋“ฑ) โŒ (์™ธ๋ถ€ memory-mapped, ์žฅ์น˜์ œ์–ด๋Š” ์•„๋‹˜)

โœ… ์™œ Block 7๋„ MMIO์ธ๊ฐ€?

0xE000_0000 ~ ์ฃผ์†Œ๋Š” Cortex-M3 ์ฝ”์–ด ๋‚ด๋ถ€ ์‹œ์Šคํ…œ ์žฅ์น˜๊ฐ€ ์œ„์น˜ํ•˜๋Š” ์˜์—ญ์ž…๋‹ˆ๋‹ค. ์˜ˆ๋ฅผ ๋“ค์–ด:

์žฅ์น˜ ์ฃผ์†Œ ์„ค๋ช…
SCB (System Control Block) 0xE000_ED00 ์ธํ„ฐ๋ŸฝํŠธ ์šฐ์„ ์ˆœ์œ„, Sleep ์ œ์–ด
NVIC (Interrupt Controller) 0xE000_E100 ์ธํ„ฐ๋ŸฝํŠธ ํ™œ์„ฑํ™”/๋น„ํ™œ์„ฑํ™”
SysTick Timer 0xE000_E010 ์‹œ์Šคํ…œ ํƒ€์ด๋จธ

์ด๋“ค์€ ๋ ˆ์ง€์Šคํ„ฐ ๋ฐฉ์‹์œผ๋กœ ๋ฉ”๋ชจ๋ฆฌ์ฒ˜๋Ÿผ ์ ‘๊ทผํ•˜๋ฏ€๋กœ Memory-Mapped I/O์ž…๋‹ˆ๋‹ค.


๐Ÿ”Ž ์ •๋ฆฌ

  • โœ… Block 2, Block 7์€ ๋ชจ๋‘ MMIO ์˜์—ญ
  • โŒ SRAM, Flash๋Š” ๋ฉ”๋ชจ๋ฆฌ์ผ ๋ฟ I/O๊ฐ€ ์•„๋‹˜
  • โŒ FSMC๋Š” ์™ธ๋ถ€ ์žฅ์น˜์™€ ์—ฐ๊ฒฐ๋˜์ง€๋งŒ ๋ ˆ์ง€์Šคํ„ฐ ์ œ์–ด์šฉ I/O๋Š” ์•„๋‹˜ (๋ฐ์ดํ„ฐ ์˜์—ญ)

ํ•„์š”ํ•˜๋‹ค๋ฉด STM32 MMIO ์ „์ฒด ์ฃผ์†Œ ์ •๋ฆฌํ‘œ๋„ ์ œ๊ณตํ•ด ๋“œ๋ฆด ์ˆ˜ ์žˆ์–ด์š”. ํŠน์ • ์˜์—ญ์ด๋‚˜ ๋ ˆ์ง€์Šคํ„ฐ๊ฐ€ ๊ถ๊ธˆํ•˜์‹ ๊ฐ€์š”?

๋‚˜์˜ ๋ง:

์‘

ChatGPT์˜ ๋ง:

์ข‹์Šต๋‹ˆ๋‹ค! STM32์—์„œ ์‚ฌ์šฉ๋˜๋Š” ์ฃผ์š” Memory-Mapped I/O (MMIO) ์ฃผ์†Œ ์ •๋ฆฌํ‘œ๋ฅผ ์•„๋ž˜์— ํ•ต์‹ฌ๋งŒ ์š”์•ฝํ•ด๋“œ๋ฆฝ๋‹ˆ๋‹ค. ์ด ํ‘œ๋Š” ์‹ค๋ฌด์—์„œ ๋ ˆ์ง€์Šคํ„ฐ ์ง์ ‘ ์ ‘๊ทผํ•˜๊ฑฐ๋‚˜ ๋””๋ฒ„๊น…ํ•  ๋•Œ ๋งค์šฐ ์œ ์šฉํ•ฉ๋‹ˆ๋‹ค.


โœ… [1] Cortex-M3 ์‹œ์Šคํ…œ MMIO (Block 7: 0xE000_0000 ~)

์žฅ์น˜ ์ฃผ์†Œ ๋ฒ”์œ„ ์„ค๋ช…
NVIC 0xE000_E100 ~ ์ธํ„ฐ๋ŸฝํŠธ ํ™œ์„ฑํ™”/๋น„ํ™œ์„ฑํ™”
SCB 0xE000_ED00 ~ ์šฐ์„ ์ˆœ์œ„, ๋ฒกํ„ฐ ํ…Œ์ด๋ธ”, SYSRESET ๋“ฑ
SysTick 0xE000_E010 ~ ์‹œ์Šคํ…œ ํƒ€์ด๋จธ
ITM/DWT/TPIU 0xE000_0000 ~ ๋””๋ฒ„๊ทธ ์ถ”์  ๋ชจ๋“ˆ

โœ… [2] ์ผ๋ฐ˜ ์ฃผ๋ณ€์žฅ์น˜ MMIO (Block 2: 0x4000_0000 ~)

โฑ ํƒ€์ด๋จธ

์žฅ์น˜ ์ฃผ์†Œ
TIM2 ~ TIM5 0x4000_0000 ~ 0x4000_3FFF
TIM6 ~ TIM14 0x4000_1000 ~ 0x4000_4FFF

๐Ÿ“ก USART / UART

์žฅ์น˜ ์ฃผ์†Œ
USART1 0x4001_3800
USART2 0x4000_4400
USART3 0x4000_4800
UART4 0x4000_4C00
UART5 0x4000_5000

๐ŸŒ€ SPI / I2C

์žฅ์น˜ ์ฃผ์†Œ
SPI1 0x4001_3000
SPI2 0x4000_3800
I2C1 0x4000_5400
I2C2 0x4000_5800

๐Ÿง  RCC / PWR

์žฅ์น˜ ์ฃผ์†Œ
RCC 0x4002_3800
PWR 0x4000_7000

๐Ÿ’ก GPIO

์žฅ์น˜ ์ฃผ์†Œ
GPIOA 0x4002_0000
GPIOB 0x4002_0400
GPIOC 0x4002_0800
GPIOD 0x4002_0C00

โœ… [3] Flash, Option Bytes, System Memory (Block 0)

์žฅ์น˜ ์ฃผ์†Œ
Flash memory 0x0800_0000 ~
System memory (bootloader) 0x1FFF_0000 ~ 0x1FFF_7A0F
Option Bytes 0x1FFF_C000 ~

๐Ÿ›  ์˜ˆ์‹œ ์ฝ”๋“œ: GPIOA์˜ PA5 ์ถœ๋ ฅ

c
๋ณต์‚ฌํŽธ์ง‘
#define RCC_AHB1ENR  (*(volatile uint32_t*)0x40023830)
#define GPIOA_MODER  (*(volatile uint32_t*)0x40020000)
#define GPIOA_ODR    (*(volatile uint32_t*)0x40020014)

void init_gpioa_pa5() {
    RCC_AHB1ENR |= (1 << 0);       // GPIOA ํด๋Ÿญ ์ธ๊ฐ€
    GPIOA_MODER |= (1 << 10);      // PA5 = Output
    GPIOA_ODR |= (1 << 5);         // PA5 High
}


์›ํ•˜์‹œ๋ฉด ์ „์ฒด MMIO ์ฃผ์†Œ ๋งต์„ PDF ํ˜น์€ ์—‘์…€๋กœ๋„ ์ •๋ฆฌํ•ด๋“œ๋ฆด ์ˆ˜ ์žˆ์–ด์š”.

์–ด๋–ค ์žฅ์น˜๋ฅผ ์œ„์ฃผ๋กœ ๋” ๋ณด๊ณ  ์‹ถ์œผ์‹ ๊ฐ€์š”? (์˜ˆ: DMA, ADC, SPI ๋“ฑ)

๋‚˜์˜ ๋ง:

PDF ๋กœ ์ค˜

ChatGPT์˜ ๋ง:

์™„๋ฃŒ๋˜์—ˆ์Šต๋‹ˆ๋‹ค. ์•„๋ž˜ ๋งํฌ์—์„œ STM32์˜ MMIO ์ฃผ์†Œ ๋งต PDF๋ฅผ ๋‹ค์šด๋กœ๋“œํ•  ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค:

๐Ÿ‘‰ stm32_mmio_map.pdf ๋‹ค์šด๋กœ๋“œ

ํ•„์š”ํ•˜์‹œ๋ฉด ADC, DMA, CAN ๋“ฑ ์ถ”๊ฐ€ ์ฃผ๋ณ€์žฅ์น˜๋„ ํฌํ•จํ•ด์„œ ํ™•์žฅํ•  ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค. ์ถ”๊ฐ€๋กœ ํฌํ•จํ• ๊นŒ์š”?

๋‚˜์˜ ๋ง:

i2c๋„ memory mapped io์ž–์•„ ๊ทธ๋Ÿฌ๋ฉด i2c๋ฅผ ํ•จ์ˆ˜๋ง๊ณ  register ์„ค์ •๋งŒ์œผ๋กœ ํ†ต์‹ ๊ฐ€๋Šฅํ•˜๋„๋ก

ChatGPT์˜ ๋ง:

๋งž์Šต๋‹ˆ๋‹ค. STM32์˜ I2C1 (0x40005400), I2C2 (0x40005800) ๋Š” ๋ชจ๋‘ Memory-Mapped I/O ๋ฐฉ์‹์œผ๋กœ ์ ‘๊ทผ ๊ฐ€๋Šฅํ•œ ๋ ˆ์ง€์Šคํ„ฐ ๊ธฐ๋ฐ˜ ์ฃผ๋ณ€์žฅ์น˜์ž…๋‹ˆ๋‹ค.

๋”ฐ๋ผ์„œ HAL ๋ผ์ด๋ธŒ๋Ÿฌ๋ฆฌ๋ฅผ ์‚ฌ์šฉํ•˜์ง€ ์•Š๊ณ ๋„ ๋ ˆ์ง€์Šคํ„ฐ๋งŒ ์ง์ ‘ ์ œ์–ดํ•˜์—ฌ I2C ํ†ต์‹ ์„ ๊ตฌํ˜„ํ•  ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค.


โœ… ๋ชฉํ‘œ: HAL ์—†์ด I2C๋ฅผ ๋ ˆ์ง€์Šคํ„ฐ๋กœ ์ง์ ‘ ์ œ์–ด

์—ฌ๊ธฐ์„œ๋Š” ๋งˆ์Šคํ„ฐ ์†ก์‹  (Master Transmit) ๊ธฐ์ค€์œผ๋กœ I2C1์„ ์‚ฌ์šฉํ•œ ์˜ˆ์ œ๋ฅผ ์„ค๋ช…ํ•ฉ๋‹ˆ๋‹ค.


โœ… 1. ๊ด€๋ จ ๋ ˆ์ง€์Šคํ„ฐ (I2C1 ๊ธฐ์ค€, 0x40005400)

์˜คํ”„์…‹ ์ด๋ฆ„ ์„ค๋ช…
0x00 I2C_CR1 Control register 1
0x04 I2C_CR2 Control register 2
0x08 I2C_OAR1 Own address register 1
0x10 I2C_DR Data register
0x14 I2C_SR1 Status register 1
0x18 I2C_SR2 Status register 2
0x1C I2C_CCR Clock control register
0x20 I2C_TRISE Maximum rise time

โœ… 2. ์˜ˆ์ œ: I2C1๋กœ 0x50 ์ฃผ์†Œ์˜ EEPROM์— 1๋ฐ”์ดํŠธ ์“ฐ๊ธฐ

๐Ÿ’ก ๊ธฐ๋ณธ ์„ค์ • (Clock & GPIO๋Š” RCC/GPIO ๋ ˆ์ง€์Šคํ„ฐ๋กœ ๋ณ„๋„ ์„ค์ •ํ•ด์•ผ ํ•จ)

c
๋ณต์‚ฌํŽธ์ง‘
#define I2C1_BASE      0x40005400
#define RCC_APB1ENR    (*(volatile uint32_t*)0x40023840)
#define RCC_AHB1ENR    (*(volatile uint32_t*)0x40023830)

#define I2C1_CR1       (*(volatile uint32_t*)(I2C1_BASE + 0x00))
#define I2C1_CR2       (*(volatile uint32_t*)(I2C1_BASE + 0x04))
#define I2C1_OAR1      (*(volatile uint32_t*)(I2C1_BASE + 0x08))
#define I2C1_DR        (*(volatile uint32_t*)(I2C1_BASE + 0x10))
#define I2C1_SR1       (*(volatile uint32_t*)(I2C1_BASE + 0x14))
#define I2C1_SR2       (*(volatile uint32_t*)(I2C1_BASE + 0x18))
#define I2C1_CCR       (*(volatile uint32_t*)(I2C1_BASE + 0x1C))
#define I2C1_TRISE     (*(volatile uint32_t*)(I2C1_BASE + 0x20))


โœ… 3. ์ดˆ๊ธฐํ™” ๋ฐ ์†ก์‹  ํ•จ์ˆ˜ (์ง์ ‘ ๊ตฌํ˜„)

c
๋ณต์‚ฌํŽธ์ง‘
void i2c1_init() {
    RCC_APB1ENR |= (1 << 21);    // I2C1 ํด๋Ÿญ ํ™œ์„ฑํ™”
    RCC_AHB1ENR |= (1 << 0);     // GPIOA ํด๋Ÿญ ํ™œ์„ฑํ™” ๋“ฑ (SCL/SDA ํ•€ ์„ค์ • ํ•„์š”)

    I2C1_CR2 = 16;               // APB1 ํด๋Ÿญ 16MHz
    I2C1_CCR = 80;               // Standard mode 100kHz
    I2C1_TRISE = 17;             // ์ตœ๋Œ€ ์ƒ์Šน ์‹œ๊ฐ„

    I2C1_CR1 |= (1 << 0);        // Peripheral Enable
}

void i2c1_start() {
    I2C1_CR1 |= (1 << 8);                    // START bit
    while (!(I2C1_SR1 & (1 << 0)));          // SB ์„ค์ •๋  ๋•Œ๊นŒ์ง€ ๋Œ€๊ธฐ
}

void i2c1_send_addr(uint8_t addr) {
    I2C1_DR = addr;
    while (!(I2C1_SR1 & (1 << 1)));          // ADDR ํ™•์ธ
    (void)I2C1_SR2;                          // SR2 ์ฝ๊ธฐ๋กœ ํด๋ฆฌ์–ด
}

void i2c1_send_data(uint8_t data) {
    while (!(I2C1_SR1 & (1 << 7)));          // TXE
    I2C1_DR = data;
    while (!(I2C1_SR1 & (1 << 2)));          // BTF
}

void i2c1_stop() {
    I2C1_CR1 |= (1 << 9);                    // STOP
}

void i2c1_write_byte(uint8_t dev_addr, uint8_t reg, uint8_t data) {
    i2c1_start();
    i2c1_send_addr(dev_addr << 1);          // Write mode
    i2c1_send_data(reg);                    // Register address
    i2c1_send_data(data);                   // Data
    i2c1_stop();
}


โœ… 4. ์ฃผ์˜์‚ฌํ•ญ

  • GPIOB ํ•€(PB6: SCL, PB7: SDA ๋“ฑ)๋„ Alternate Function ์„ค์ • ํ•„์š”
  • AF4๋กœ ์„ค์ • (STM32F4 ๊ธฐ์ค€)
  • APB1 ํด๋Ÿญ ์ฃผํŒŒ์ˆ˜์— ๋”ฐ๋ผ CCR, TRISE ๊ฐ’ ๋ณ€๊ฒฝ ํ•„์š”

โœ… ์š”์•ฝ

ํ•ญ๋ชฉ ๋‚ด์šฉ
๊ตฌ์กฐ I2C๋Š” MMIO ๋ ˆ์ง€์Šคํ„ฐ๋ฅผ ํ†ตํ•ด ์ง์ ‘ ์ œ์–ด ๊ฐ€๋Šฅ
์ฃผ์†Œ I2C1 = 0x40005400, I2C2 = 0x40005800
์žฅ์  HAL ๋ฏธ์‚ฌ์šฉ โ†’ ์ฝ”๋“œ ๊ฒฝ๋Ÿ‰ํ™”, ๋น ๋ฅธ ์ œ์–ด
์œ„ํ—˜ ์˜ค๋ฅ˜ ์ฒ˜๋ฆฌ, ํƒ€์ด๋ฐ, ACK ์ฒดํฌ ๋“ฑ ์ˆ˜๋™ ์ฒ˜๋ฆฌ ํ•„์š”

ํ•„์š”ํ•˜๋ฉด “I2C ์ˆ˜์‹ ”์ด๋‚˜ “EEPROM ์ฝ๊ธฐ”, “ACK ๊ฒ€์‚ฌ” ๋“ฑ๋„ ์ถ”๊ฐ€๋กœ ์ž‘์„ฑํ•ด๋“œ๋ฆด ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค. ์–ด๋–ค ์ž‘์—…๋„ ํ•ด๋ณด์‹œ๊ฒ ์–ด์š”?

๋‚˜์˜ ๋ง:

์ฝ”๋“œ์— ์ฃผ์„์„ ๋‹ฌ์•„์•ผ์ง€

ChatGPT์˜ ๋ง:

๋ฌผ๋ก ์ž…๋‹ˆ๋‹ค. ์•„๋ž˜๋Š” HAL ์—†์ด ๋ ˆ์ง€์Šคํ„ฐ๋งŒ์œผ๋กœ I2C1 ๋งˆ์Šคํ„ฐ ์†ก์‹ ์„ ๊ตฌํ˜„ํ•œ ์˜ˆ์ œ ์ฝ”๋“œ์— ์ž์„ธํ•œ ์ฃผ์„์„ ์ถ”๊ฐ€ํ•œ ๋ฒ„์ „์ž…๋‹ˆ๋‹ค. ์ด ์ฝ”๋“œ๋Š” STM32์—์„œ I2C๋ฅผ ์ง์ ‘ ์ œ์–ดํ•˜์—ฌ 0x50 ์ฃผ์†Œ์˜ ์Šฌ๋ ˆ์ด๋ธŒ์— ๋ฐ์ดํ„ฐ๋ฅผ ์“ฐ๋Š” ๋™์ž‘์ž…๋‹ˆ๋‹ค.


โœ… ๋ ˆ์ง€์Šคํ„ฐ ์ •์˜ ๋ฐ ์ดˆ๊ธฐํ™” ํ•จ์ˆ˜

c
๋ณต์‚ฌํŽธ์ง‘
// RCC ๊ด€๋ จ ๋ ˆ์ง€์Šคํ„ฐ: ํด๋Ÿญ ์„ค์ •์šฉ
#define RCC_APB1ENR    (*(volatile uint32_t*)0x40023840)  // APB1 ๋ฒ„์Šค (I2C ํด๋Ÿญ)
#define RCC_AHB1ENR    (*(volatile uint32_t*)0x40023830)  // AHB1 ๋ฒ„์Šค (GPIO ํด๋Ÿญ)

// I2C1 ๋ฒ ์ด์Šค ์ฃผ์†Œ ๋ฐ ๋ ˆ์ง€์Šคํ„ฐ ์ •์˜
#define I2C1_BASE      0x40005400
#define I2C1_CR1       (*(volatile uint32_t*)(I2C1_BASE + 0x00))  // ์ œ์–ด 1
#define I2C1_CR2       (*(volatile uint32_t*)(I2C1_BASE + 0x04))  // ์ œ์–ด 2 (ํด๋Ÿญ ์„ค์ •)
#define I2C1_OAR1      (*(volatile uint32_t*)(I2C1_BASE + 0x08))  // Own Address 1
#define I2C1_DR        (*(volatile uint32_t*)(I2C1_BASE + 0x10))  // ๋ฐ์ดํ„ฐ ๋ ˆ์ง€์Šคํ„ฐ
#define I2C1_SR1       (*(volatile uint32_t*)(I2C1_BASE + 0x14))  // ์ƒํƒœ 1
#define I2C1_SR2       (*(volatile uint32_t*)(I2C1_BASE + 0x18))  // ์ƒํƒœ 2
#define I2C1_CCR       (*(volatile uint32_t*)(I2C1_BASE + 0x1C))  // ํด๋Ÿญ ์ œ์–ด
#define I2C1_TRISE     (*(volatile uint32_t*)(I2C1_BASE + 0x20))  // ์ตœ๋Œ€ ์ƒ์Šน ์‹œ๊ฐ„


โœ… I2C1 ์ดˆ๊ธฐํ™”

c
๋ณต์‚ฌํŽธ์ง‘
void i2c1_init() {
    RCC_APB1ENR |= (1 << 21);    // I2C1 ํด๋Ÿญ ํ™œ์„ฑํ™”
    RCC_AHB1ENR |= (1 << 1);     // GPIOB ํด๋Ÿญ ํ™œ์„ฑํ™” (PB6=SCL, PB7=SDA)

    I2C1_CR2 = 16;               // APB1 ํด๋Ÿญ ์ฃผํŒŒ์ˆ˜ ์„ค์ • (16MHz)
    I2C1_CCR = 80;               // 100kHz ์„ค์ • (Standard Mode = 16MHz / (2*CCR))
    I2C1_TRISE = 17;             // ์ตœ๋Œ€ ์ƒ์Šน ์‹œ๊ฐ„ = 1000ns ๊ธฐ์ค€ โ†’ TRISE = Freq(MHz) + 1

    I2C1_CR1 |= (1 << 0);        // I2C1 Peripheral Enable
}


โœ… I2C1 ๋™์ž‘ ํ•จ์ˆ˜๋“ค (START โ†’ ์ฃผ์†Œ ์ „์†ก โ†’ ๋ฐ์ดํ„ฐ ์ „์†ก โ†’ STOP)

c
๋ณต์‚ฌํŽธ์ง‘
void i2c1_start() {
    I2C1_CR1 |= (1 << 8);                    // START ๋น„ํŠธ ์„ค์ •
    while (!(I2C1_SR1 & (1 << 0)));          // SB (Start Bit ์„ค์ •๋จ) ํ”Œ๋ž˜๊ทธ ๋Œ€๊ธฐ
}

void i2c1_send_addr(uint8_t addr) {
    I2C1_DR = addr;                          // ์Šฌ๋ ˆ์ด๋ธŒ ์ฃผ์†Œ (LSB = 0 for Write)
    while (!(I2C1_SR1 & (1 << 1)));          // ADDR ํ”Œ๋ž˜๊ทธ ๋Œ€๊ธฐ (์ฃผ์†Œ ์ „์†ก ์™„๋ฃŒ)
    (void)I2C1_SR2;                          // SR2 ์ฝ๊ธฐ๋กœ ADDR ํด๋ฆฌ์–ด
}

void i2c1_send_data(uint8_t data) {
    while (!(I2C1_SR1 & (1 << 7)));          // TXE (์ „์†ก ๋ฒ„ํผ Empty) ๋Œ€๊ธฐ
    I2C1_DR = data;                          // ๋ฐ์ดํ„ฐ ์ „์†ก
    while (!(I2C1_SR1 & (1 << 2)));          // BTF (Byte Transfer Finished) ๋Œ€๊ธฐ
}

void i2c1_stop() {
    I2C1_CR1 |= (1 << 9);                    // STOP ๋น„ํŠธ ์„ค์ • โ†’ ํ†ต์‹  ์ข…๋ฃŒ
}


โœ… I2C1 ๋งˆ์Šคํ„ฐ ์†ก์‹  (1 ๋ฐ”์ดํŠธ)

c
๋ณต์‚ฌํŽธ์ง‘
void i2c1_write_byte(uint8_t dev_addr, uint8_t reg, uint8_t data) {
    i2c1_start();                            // START ์‹ ํ˜ธ ๋ฐœ์ƒ
    i2c1_send_addr(dev_addr << 1);          // ์Šฌ๋ ˆ์ด๋ธŒ ์ฃผ์†Œ ์ „์†ก (Write ๋ชจ๋“œ)
    i2c1_send_data(reg);                    // ๋ ˆ์ง€์Šคํ„ฐ ์ฃผ์†Œ ์ „์†ก (๋ณดํ†ต EEPROM์€ ์ฃผ์†Œ ์ง€์ • ํ•„์š”)
    i2c1_send_data(data);                   // ์‹ค์ œ ์ „์†กํ•  ๋ฐ์ดํ„ฐ ๋ฐ”์ดํŠธ
    i2c1_stop();                             // STOP์œผ๋กœ ์ข…๋ฃŒ
}


โœ… ์‚ฌ์šฉ ์˜ˆ์‹œ

c
๋ณต์‚ฌํŽธ์ง‘
i2c1_init();                                 // I2C1 ์ดˆ๊ธฐํ™”
i2c1_write_byte(0x50, 0x10, 0xAB);           // EEPROM 0x50, ์ฃผ์†Œ 0x10์— 0xAB ์“ฐ๊ธฐ


โš ๏ธ ์ฃผ์˜์‚ฌํ•ญ

  • ๋ฐ˜๋“œ์‹œ GPIO (PB6, PB7 ๋“ฑ)๋ฅผ Alternate Function์œผ๋กœ ์„ค์ •ํ•ด์•ผ ๋™์ž‘ํ•ฉ๋‹ˆ๋‹ค.
  • ์˜ค๋ฅ˜ ํ•ธ๋“ค๋ง(ACK ์‹คํŒจ ๋“ฑ)์€ ์œ„ ์ฝ”๋“œ์— ํฌํ•จ๋˜์–ด ์žˆ์ง€ ์•Š์œผ๋ฉฐ, ์‹ค์ „์—์„œ๋Š” ํƒ€์ž„์•„์›ƒ ์ฒ˜๋ฆฌ, ์—๋Ÿฌ ํ”Œ๋ž˜๊ทธ ํ™•์ธ์ด ์ถ”๊ฐ€๋˜์–ด์•ผ ํ•ฉ๋‹ˆ๋‹ค.
  • ๋น ๋ฅด๊ฒŒ ์“ฐ๊ณ  ๋ฐ˜๋ณต์ ์œผ๋กœ ์†ก์‹ ํ•  ๊ฒฝ์šฐ, BTF ํ™•์ธ ์—†์ด Stop์„ ๋‚ด๋ฆฌ๋ฉด ๋ฌธ์ œ๊ฐ€ ์ƒ๊ธธ ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค.

ํ•„์š”ํ•˜๋‹ค๋ฉด ์ฝ๊ธฐ(Receive) ์ฒ˜๋ฆฌ, EEPROM ์—ฐ์† ์“ฐ๊ธฐ, ACK ์˜ค๋ฅ˜ ์ฒ˜๋ฆฌ, DMA ์—ฐ๋™ ๋ฒ„์ „๋„ ๋„์™€๋“œ๋ฆด ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค. ์–ด๋–ค ์ž‘์—…์„ ๋” ํ•ด๋ณผ๊นŒ์š”?

๋‚˜์˜ ๋ง:

i2c ํ”„๋กœํ† ์ฝœ ์ž์„ธํžˆ ์„ค๋ช…

ChatGPT์˜ ๋ง:

์ข‹์Šต๋‹ˆ๋‹ค. ์•„๋ž˜๋Š” I2C(Inter-Integrated Circuit) ํ”„๋กœํ† ์ฝœ์— ๋Œ€ํ•œ ํ•ต์‹ฌ ๊ฐœ๋…, ๋™์ž‘ ์ˆœ์„œ, ์‹ ํ˜ธ ๊ตฌ์กฐ, ์ƒํƒœ ํ”Œ๋ž˜๊ทธ ๋“ฑ์„ ํฌํ•จํ•œ ์™„์ „ํ•œ ์„ค๋ช…์ž…๋‹ˆ๋‹ค.


๐Ÿ“Œ I2C๋ž€?

I2C (Inter-Integrated Circuit) ๋Š” NXP(่ˆŠ Philips) ๊ฐ€ ๋งŒ๋“  ์–‘๋ฐฉํ–ฅ 2์„ ์‹ ์ง๋ ฌ ํ†ต์‹  ํ”„๋กœํ† ์ฝœ์ž…๋‹ˆ๋‹ค.

  • ๐Ÿงท ์„  2๊ฐœ๋งŒ ์‚ฌ์šฉ:
    • SCL: Serial Clock Line
    • SDA: Serial Data Line
  • ๐Ÿงญ ๋งˆ์Šคํ„ฐ/์Šฌ๋ ˆ์ด๋ธŒ ๊ตฌ์กฐ

    ํ•˜๋‚˜์˜ ๋งˆ์Šคํ„ฐ๊ฐ€ ์‹œ๊ณ„๋ฅผ ์ œ์–ดํ•˜๊ณ , ์Šฌ๋ ˆ์ด๋ธŒ๊ฐ€ ์‘๋‹ตํ•ฉ๋‹ˆ๋‹ค.

  • ๐Ÿ’ฌ ์ฃผ์†Œ ๊ธฐ๋ฐ˜ ํ†ต์‹ :

    ์Šฌ๋ ˆ์ด๋ธŒ๋Š” 7๋น„ํŠธ ๋˜๋Š” 10๋น„ํŠธ ์ฃผ์†Œ๋ฅผ ๊ฐ€์ง (์ผ๋ฐ˜์ ์œผ๋กœ 7๋น„ํŠธ)


๐Ÿงฉ I2C ๊ธฐ๋ณธ ํ†ต์‹  ๊ตฌ์„ฑ์š”์†Œ

sql
๋ณต์‚ฌํŽธ์ง‘
START โ†’ ์ฃผ์†Œ(7bit) + R/W โ†’ ACK โ†’ ๋ฐ์ดํ„ฐ ์ „์†ก โ†’ ACK โ†’ STOP

  • START (S): SDA๊ฐ€ High โ†’ Low๋กœ ๋–จ์–ด์งˆ ๋•Œ, SCL์€ High
  • STOP (P): SDA๊ฐ€ Low โ†’ High๋กœ ์˜ฌ๋ผ๊ฐˆ ๋•Œ, SCL์€ High
  • ACK/NACK: ์ˆ˜์‹ ์ž๊ฐ€ ๋ฐ์ดํ„ฐ๋ฅผ ์ •์ƒ ์ˆ˜์‹ ํ–ˆ์Œ์„ ์•Œ๋ฆฌ๋Š” ์‹ ํ˜ธ (ACK: 0, NACK: 1)

๐Ÿงพ ๋ฐ์ดํ„ฐ ์ „์†ก ํ”„๋ ˆ์ž„ ๊ตฌ์กฐ

๊ตฌ๋ถ„ ๋น„ํŠธ์ˆ˜ ์„ค๋ช…
Start 1 ์‹œ์ž‘ ์กฐ๊ฑด
Address 7 ์Šฌ๋ ˆ์ด๋ธŒ ์ฃผ์†Œ
R/W 1 0: Write, 1: Read
ACK 1 ์ˆ˜์‹ ์ž์˜ ์‘๋‹ต
Data 8 ๋ณด๋‚ผ ๋ฐ์ดํ„ฐ
ACK 1 ์ˆ˜์‹ ์ž์˜ ์‘๋‹ต
๋ฐ˜๋ณต ๊ฐ€๋Šฅ
Stop 1 ์ข…๋ฃŒ ์กฐ๊ฑด

๐Ÿ”„ I2C ์“ฐ๊ธฐ(Write) ์‹œํ€€์Šค (๋งˆ์Šคํ„ฐ ๊ธฐ์ค€)

css
๋ณต์‚ฌํŽธ์ง‘
[S] โ†’ [ADDR + 0] โ†’ [ACK] โ†’ [DATA1] โ†’ [ACK] โ†’ [DATA2] โ†’ [ACK] โ†’ [P]

์˜ˆ: EEPROM์— 0x50 ์ฃผ์†Œ๋กœ 0xAB ์ „์†ก

  1. START ์กฐ๊ฑด ๋ฐœ์ƒ
  1. ์Šฌ๋ ˆ์ด๋ธŒ ์ฃผ์†Œ ์ „์†ก (0x50 << 1 | 0 = 0xA0)
  1. ์Šฌ๋ ˆ์ด๋ธŒ๊ฐ€ ACK ๋ณด๋ƒ„
  1. ๋ฐ์ดํ„ฐ ๋ฐ”์ดํŠธ ์ „์†ก (0xAB)
  1. ์Šฌ๋ ˆ์ด๋ธŒ๊ฐ€ ACK ๋ณด๋ƒ„
  1. STOP ๋ฐœ์ƒ

๐Ÿ” I2C ์ฝ๊ธฐ(Read) ์‹œํ€€์Šค

css
๋ณต์‚ฌํŽธ์ง‘
[S] โ†’ [ADDR + 0] โ†’ [ACK] โ†’ [MEM_ADDR] โ†’ [ACK] โ†’ [S repeated] โ†’ [ADDR + 1] โ†’ [ACK] โ†’ [DATA] โ†’ [NACK] โ†’ [P]

  • 2๊ฐœ์˜ START ์กฐ๊ฑด ์‚ฌ์šฉ (Repeated START)
  • ๋งˆ์ง€๋ง‰ ๋ฐ”์ดํŠธ๋Š” NACK์œผ๋กœ ๋งˆ๋ฌด๋ฆฌ

โœ… I2C ์ƒํƒœ ํ”Œ๋ž˜๊ทธ ์˜ˆ์‹œ (STM32 ๊ธฐ์ค€)

ํ”Œ๋ž˜๊ทธ ์„ค๋ช… ์œ„์น˜
SB (Start Bit) START ์‹ ํ˜ธ ๋ฐœ์ƒ๋จ SR1[0]
ADDR ์ฃผ์†Œ ์ „์†ก ์™„๋ฃŒ SR1[1]
BTF ๋ฐ”์ดํŠธ ์ „์†ก ์™„๋ฃŒ SR1[2]
TXE ๋ฐ์ดํ„ฐ ๋ ˆ์ง€์Šคํ„ฐ ๋น„์–ด ์žˆ์Œ SR1[7]
RXNE ์ˆ˜์‹  ๋ฐ์ดํ„ฐ ์ค€๋น„ ์™„๋ฃŒ SR1[6]
STOPF ์Šฌ๋ ˆ์ด๋ธŒ๊ฐ€ STOP ๊ฐ์ง€ SR1[4]

๐Ÿง  ํŠน์ง• ์š”์•ฝ

ํ•ญ๋ชฉ ์„ค๋ช…
๐Ÿงท ์ „์„  2๊ฐœ (SDA, SCL)
๐ŸŽ› ๊ตฌ์กฐ ๋งˆ์Šคํ„ฐ-์Šฌ๋ ˆ์ด๋ธŒ
โฑ ์†๋„ ํ‘œ์ค€(100kHz), ํŒจ์ŠคํŠธ(400kHz), ํŒจ์ŠคํŠธํ”Œ๋Ÿฌ์Šค(1MHz), ํ•˜์ด์Šคํ”ผ๋“œ(3.4MHz)
๐Ÿงช ์—๋Ÿฌ ์ฒ˜๋ฆฌ ์Šฌ๋ ˆ์ด๋ธŒ๊ฐ€ ์‘๋‹ตํ•˜์ง€ ์•Š์œผ๋ฉด ACK ์—†์Œ, ํƒ€์ž„์•„์›ƒ ํ•„์š”
๐Ÿ”ง ์žฅ์  ํšŒ๋กœ ๋‹จ์ˆœ, ์ฃผ์†Œ ๊ธฐ๋ฐ˜, ๋ฉ€ํ‹ฐ์Šฌ๋ ˆ์ด๋ธŒ ์ง€์›
๐Ÿ”ฉ ๋‹จ์  SPI๋ณด๋‹ค ๋А๋ฆผ, ํ”„๋กœํ† ์ฝœ ๋ณต์žก๋„ โ†‘

๐Ÿ“ ์‹ค์ œ ํ†ต์‹  ํŒŒํ˜• ์˜ˆ์‹œ

text
๋ณต์‚ฌํŽธ์ง‘
SCL:  __|โ€พ|__|โ€พ|__|โ€พ|__|โ€พ|__|โ€พ|__|โ€พ|__|โ€พ|__|โ€พ|__
SDA:  --\___0_1_0_1_0_0_0/---ACK---data_byte---/
        START    7bit ADDR + W

Posted in ํ”„๋กœ๊ทธ๋ž˜๋ฐ.

๋‹ต๊ธ€ ๋‚จ๊ธฐ๊ธฐ

์ด๋ฉ”์ผ ์ฃผ์†Œ๋Š” ๊ณต๊ฐœ๋˜์ง€ ์•Š์Šต๋‹ˆ๋‹ค. ํ•„์ˆ˜ ํ•„๋“œ๋Š” *๋กœ ํ‘œ์‹œ๋ฉ๋‹ˆ๋‹ค